1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which data read performance of a memory cell is improved.
2. Description of the Related Art
To realize a high integration and a large capacity of memory cells, the following semiconductor memory devices are proposed ((1) 1991, IEEE ISSCC DIGEST 0F TECHNICAL PAPERS vol. 34, p. 106, TAM6.2, (2) 1993, IEEE ISSCC DIGEST 0F TECHNICAL PAPERS vol. 36, p. 46, WP3.31). The semiconductor memory devices are constructed by arranging a plurality of memory cell units, each of which has a plurality of dynamic random access memory cells which are connected in series, in an array and one end of the memory cell unit is connected to the bit line. This device is effective in improving the degree of integration, since the number of bit line contacts can be decreased in accordance with the number of series-connected memory cells.
Devices of this sort, however, have the following problems.
Since memory cells are connected in series, it is necessary to read out data from a memory cell unit sequentially from a memory cell closest to a bit line contact and to write data from a memory cell farthest from the bit line contact. Accordingly, read and rewrite actions take a long time.
Also, a current tendency is to require a page read operation which sequentially reads out consecutive column addresses. Unfortunately, in conventional devices the capacity of pages capable of being successively read out is small. Additionally, when the operation proceeds on to each subsequent page after reading out one page, it is necessary to activate memory cells and perform data detection and amplification using a sense amplifier, resulting in a long operation time. These disadvantages apply not only to devices having a memory cell unit in which a plurality of memory cells are connected in series but also to devices in which memory cells are connected to bit lines, a plurality of sense amplifiers are shared by a plurality of bit lines, and data on the bit lines are time-divisionally read out.
As described above, reads and writes take a long time in conventional semiconductor memory devices, particularly in semiconductor memory devices having a memory cell unit in which a plurality of memory cells are connected in series.